(1) Field of the Invention
The present invention relates to methods used to fabricate semiconductor devices, and more specifically to a method used to fabricate a dynamic random access memory (DRAM) device featuring increased capacitance and improved capacitor top plate to bit line overlay margin.
(2) Description of Prior Art
Major objectives of DRAM manufacturers have been to increase DRAM density while still maintaining or increasing capacitance. To achieve increased DRAM density, or to increase the number of DRAM cells on a specific semiconductor chip, advanced photolithographic and dry etching disciplines have to employed. The smaller features obtained via advances in photolithographic exposure tools and procedures, as well as via advances in dry etching tools and processes, have allowed the attainment of DRAM cells comprised with sub-quarter micron features, to be routinely obtained, satisfying the density objectives. However the use of smaller features can negatively influence the attainment of other DRAM objectives such as the desired capacitance increases. For DRAM designs using stacked capacitor structures the objective of increased capacitance has been accomplished via increasing the height of the capacitor structure. However the path to taller capacitor storage nodes structures entails the use of thick insulator layers, subsequently resulting in a high aspect ratio for a bit line contact opening, for capacitor under bit line (CUB) designs. In addition the more tightly packed DRAM features reduce the space needed for adequate isolation between the bit line contact, and storage node structures, while demanding stringent overlay requirements.
This invention will describe a novel procedure and design for a DRAM cell, in which cell capacitance can be increased without increasing the height of the storage node structures, as well as providing adequate isolation between, and relaxing the overlay margin, bit line and storage node structures as used in a CUB design. A novel top plate definition sequence, employing photolithographic, dry etching and chemical mechanical polishing (CMP) procedures, are described allowing both the desired increased capacitance to be accomplished without increasing the aspect ratio for the opening of the bit line contact hole. Prior art such as Chen et al, in U.S. Pat. No. 5,956,587, as well as Ajika et al, in U.S. Pat. No. 5,798,289, offer processes for fabricating capacitor structures. These prior arts however do not describe the novel process sequence described in this present invention in which a combination of photolithographic, dry etching, and CMP processes are used to form a capacitor structure with the desired increased capacitance objectives.